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? semiconductor components industries, llc, 2006 december, 2017 ? rev. 4 1 publication order number: fan53526/d fan53526 3.0 a, 2.4 mhz, digitally programmable tinybuck regulator descriptions the fan53526 is a step ? down switching voltage regulator that delivers a digitally programmable output from an input voltage supply of 2.5 v to 5.5 v. the output voltage is programmed through an i 2 c interface capable of operating up to 3.4 mhz. using a proprietary architecture with synchronous rectification, the fan53526 is capable of delivering 3.0 a continuous at over 80% efficiency, maintaining that efficiency at load currents as low as 10 ma. the regulator operates at a nominal fixed frequency of 2.4 mhz, which reduces the value of the external components. additional output capacitance can be added to improve regulation during load transients without affecting stability. at moderate and light loads, pulse frequency modulation (pfm) is used to operate in power ? save mode with a typical quiescent current of 50 a at room temperature. even with such a low quiescent current, the part exhibits excellent transient response during large load swings. at higher loads, the system automatically switches to fixed ? frequency control, operating at 2.4 mhz. in shutdown mode, the supply current drops below 1 a, reducing power consumption. pfm mode can be disabled if fixed frequency is desired. the fan53526 is available in a 15 ? bump, 1.310 mm x 2.015 mm, 0.4 mm ball pitch wlcsp. features ? fixed ? frequency operation: 2.4 mhz ? best ? in ? class lo ad transient ? continuous output current capability: 3.0 a ? 2.5 v to 5.5 v input voltage range ? digitally programmable output voltage: ? ? 0. 600 v to 1.39375 v in 6.25 mv steps ? programmable slew rate for voltage transitions ? i 2 c ? compatible interface up to 3.4 mbps ? pfm mode for high efficiency in light - load ? quiescent current in pfm mode: 50 a (typical) ? input under ? voltage lockout (uvlo) ? thermal shutdown and overload protection ? 1 5 ? bump wafer ? level chip scale package (wlcsp) applications ? application, graphic, and dsp processors ? arm , tegra , omap , novathor, armada , krait , etc. ? hard disk drives, lpddr3, lpddr4 ? tablets, netbooks, ultra ? mobile pcs ? smart phones ? gaming devices www. onsemi.com see detailed ordering and shipping information on page 2 of this data sheet. ordering information wlcsp ? 15 case 567qs pgnd agnd vsel sda en scl vout agnd pgnd sw vin c1 b1 a1 a2 c3 b3 a3 c2 d1 d3 d2 b2 e1 e3 e2 pin configuration marking diagram 1, 2 = two alphanumeric characters for device mark kk = two alphanumeric characters for lot rune code mark . = pin 1 indicator x = alphabetical year code y= 2 ? weeks date code z = assembly plant code 1 pin ? 1 mark 2kk xyz
fan53526 www. onsemi.com 2 fan 53526 sw c out l1 pvin pgnd c in vout agnd load vsel scl sda en c in_load c by figure 1. typical application table 1. ordering information part number power ? up defaults dvs range / step size i 2 c slave address temperature range package packing method device marking vsel0 vsel1 fan53526uc84x 1.125 1.125 0.600 v to 1.39375 v / 6.25 mv c0 ? 40 to 85 c wlcsp tape & reel f7 fan53526uc89x 1.15625 1.15625 cl fan53526uc100x 1.225 1.225 f9 fan53526uc106x 1.2625 1.2625 c7 fan53526uc128x 1.20 1.20 f3 fan53526uc00x 0.60 0.60 ga FAN53526UC64X 1.00 1.00 gg fan53526uc88x 1.15 1.15 lm fan53526uc288x 1.15 1.15 c2 ln fan53526uc168x 1.125 1.125 fr recommended external components table 2. recommended external components for 3.0 a maximum load current component description vendor parameter typ. unit l1 330 nh, 2016 case size see table 3 l1 alternative ( note 1 ) 470 nh 2016 case size c out1, c out2 47 f, 6.3 v, x5r, 0603 grm188r60j476me15 (murata) c 47 f c out1, c out2 alternative (note 1) 22 f, 10 v, x5r, 0603 cl10a226mp8nunb (samsung) c 22 c in 1 piece; 4.7 f, 10 v, x5r, 0603 c1608x5r1a475k (tdk) c 4.7 c by 1 piece; 100 nf, 6.3v, x5r, 0201 grm033r60j104ke19d (murata) c 100 nf 1. c out alternative and l1 alternative can be used if not following reference design. c by is recommended to reduce any high frequency component on vin bus. c by is optional and used to filter any high frequency component on vin bus.
fan53526 www. onsemi.com 3 table 3. recommended inductors manufacturer part # l (nh) dcr (m typ.) i sat (note 2) l w h toko dfe201612e ? r33n 330 15 7.0 2.0 1.6 1.2 toko dfe201612e ? r47n 470 21 6.1 2.0 1.6 1.2 cyntek pife20161b ? r47ms ? 39 470 30 3.1 2.0 1.6 1.2 semco cigt201610umr47mne 470 30 4.0 2.0 1.6 0.9 semco cigt201610umr47mne 470 33 3.0 2.0 1.2 0.9 2. i sat where the dc current drops the inductance by 30%. pin configuration pgnd agnd vsel sda en scl vout agnd pgnd sw vin c1 b1 a1 a2 c3 b3 a3 c2 d1 d3 d2 b2 e1 e3 e2 figure 2. pin configuration c1 b1 a1 c3 b3 a3 a2 c2 d1 d3 d2 b2 e1 e3 e2 top view bottom view table 4. pin definitions pin # name description d1 vsel voltage select. when this pin is low, v out is set by the vsel0 register. when this pin is high, v out is set by the vsel1 register. polarity of pin in conjunction with the mode bits in the control register 02h, will select forced pwm or auto pfm/pwm mode of operation. vsel0=auto pfm, and vsel1=fpwm. the vsel pin has an internal pull ? down resistor (250k ) , which is only acti- vated with a logic low. d2 en enable. the device is in shutdown mode when this pin is low. device keeps register content when en pin is low. the en pin has an internal pull ? down resistor (250k ) , which is only activat- ed with a logic low. e2 scl i 2 c serial clock d3 sda i 2 c serial data e3 vout vout. sense pin for v out . connect to c out . a3, b3, c2 pgnd power ground. the low ? side mosfet is referenced to this pin. c in and c out should be returned with a minimal path to these pins. c3, e1 agnd analog ground. all signals are referenced to this pin. avoid routing high dv/dt ac currents through this pin. a1, b1, c1 vin power input voltage. connect to the input power source. connect to c in with minimal path. a2, b2 sw switching node. connect to the inductor.
fan53526 www. onsemi.com 4 absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. table 5. absolute maximum ratings symbol parameter parameter min max unit v in voltage on sw, vin pins ic not switching ? 0.3 7.0 v ic switching ? 0.3 6.5 voltage on en pin ? 0.3 vin (note 3) voltage on all other pins ic not switching ? 0.3 vin (note 3) v out voltage on vout pin ? 0.3 6.5 v v inov_slew maximum slew rate of v in > 6.5v, pwm switching 100 v/ms esd human body model, ansi/esda/jedec js ? 001 ? 2012 2000 v charged device model per jesd22 ? c101 1000 t j junction temperature ? 40 +150 c t stg storage temperature ? 65 +150 c t l lead soldering temperature, 10 seconds +260 c 3. lesser of 7v or v in + 0.3 v. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. on semiconductor does not recommend exceeding them or designing to absolute maximum ratings. table 6. recommended operating conditions symbol parameter min. typ. max. unit v in supply voltage range 2.5 5.5 v i out output current 0 3.0 a t a operating ambient temperature ? 40 +85 c t j operating junction temperature ? 40 +125 c table 7. thermal properties symbol parameter min. typ. max. unit ja junction ? to ? ambient thermal resistance (note 4) 42 c/w 4. junction ? to ? ambient thermal resistance is a function of application and board layout. this data is simulated with four ? layer 2s2p boards with vias in accordance to jesd51 ? jedec standard. special attention must be paid not to exceed the junction temperature
fan53526 www. onsemi.com 5 electrical characteristics table 8. electrical characteristics minimum and maximum values are at v in =3.6 v, t a =-40c to +85c, unless otherwise noted. typical values are at t a =25c, v in =3.6 v, and en=high. vout = 1.15625 v. symbol parameter condition min. typ. max. unit power supplies i q quiescent current i load =0 50 a i load =0, mode bit=1 (forced pwm) 15 ma i sd h/w shutdown supply current en=gnd 0.1 3.0 a s/w shutdown supply current en=v in , buck_enx=0, 2.5 v v in 5.5 v 2 12 a v uvlo under ? voltage lockout threshold v in rising 2.32 2.45 v v uvhyst under ? voltage lockout hysteresis 350 mv en, vsel, sda, scl v ih high ? level input voltage 2.5 v v in 5.5 v 1.1 v v il low ? level input voltage 2.5 v v in 5.5 v 0.4 v i in input bias current input tied to gnd or vin 0.01 1.00 a v out regulation v reg v out dc accuracy 2.5 v v in 5.5 v, v out from mini- mum to maximum, i out(dc) =0 to 3.0 a, auto pfm/pwm ? 2.5 2.5 % 2.5 v v in 5.5 v, v out from mini- mum to maximum, i out(dc) =0 to 3.0 a, forced pwm ? 1.5 1.5 v in =3.8 v, v out =0.6 v, i out(dc) =500 ma, auto pfm/pwm ? 2.3 ? 0.5 ? 14 ? 3 mv v out i load load regulation i out(dc) =1 to 3 a ? 0.01 %/a v out v in line regulation 2.5 v v in 5.5 v, i out(dc) =1.5 a 0.01 %/a v trsp transient response i load step 0.01 a ? 1.5 a, t r =t f =200 ns, v out =1.15625 v 50 mv i load step 0 a ? 500 ma, t r =t f =100 ns, v in =3.8 v, v out =0.6 v 16 power switch / protection i limpk p ? mos peak current limit 4.00 4.75 5.50 a t limit thermal shutdown 150 c t hyst thermal shutdown hysteresis 17 c v sdwn input ovp shutdown rising threshold 6.15 v falling threshold 5.50 5.73 frequency control f sw oscillator frequency 2.05 2.40 2.75 mhz dac resolution 7 bits differential nonlinearity (5) 0.5 lsb
fan53526 www. onsemi.com 6 table 8. electrical characteristics minimum and maximum values are at v in =3.6 v, t a =-40c to +85c, unless otherwise noted. typical values are at t a =25c, v in =3.6 v, and en=high. vout = 1.15625 v. symbol unit max. typ. min. condition parameter soft ? start t ss regulator enable to regulated v out r load > 5 , v out =1.15625v, from en rising edge to 95% v out 150 s 5. monotonicity assured by design. table 9. i 2 c timing specifications minimum and maximum values are at v in =3.6 v, t a =-40c to +85c, unless otherwise noted. typical values are at t a =25c, v in =3.6 v, and en=high. vout = 1.15625 v. symbol parameter condition min. typ. max. unit power supplies f scl scl clock frequency standard mode 100 khz fast mode 400 fast mode plus 1000 high ? speed mode, c b 100 pf 3400 high ? speed mode, c b 400 pf 1700 t buf bus ? free time between stop and start conditions standard mode 4.7 s fast mode 1.3 fast mode plus 0.5 t hd;sta start or repeated start hold time standard mode 4 s fast mode 600 ns fast mode plus 260 high ? speed mode 160 t low scl low period standard mode 4.7 s fast mode 1.3 fast mode plus 0.5 high ? speed mode, c b 100 pf 160 ns high ? speed mode, c b 400 pf 320 t high scl high period standard mode 4 s fast mode 600 ns fast mode plus 260 high ? speed mode, c b 100 pf 60 high ? speed mode, c b 400 pf 120 t su;sta repeated start setup time standard mode 4.7 s fast mode 600 ns fast mode plus 260 high ? speed mode 160
fan53526 www. onsemi.com 7 table 9. i 2 c timing specifications minimum and maximum values are at v in =3.6 v, t a =-40c to +85c, unless otherwise noted. typical values are at t a =25c, v in =3.6 v, and en=high. vout = 1.15625 v. symbol unit max. typ. min. condition parameter power supplies t su;dat data setup time standard mode 250 ns fast mode 100 fast mode plus 50 high ? speed mode 10 t hd;dat data hold time standard mode 0 3.45 s fast mode 0 900 ns fast mode plus 0 450 high ? speed mode, c b 100 pf 0 70 high ? speed mode, c b 400 pf 0 150 t rcl scl rise time standard mode 20+0.1c b 1000 ns fast mode 20+0.1c b 300 fast mode plus 20+0.1c b 120 high ? speed mode, c b 100 pf 10 80 high ? speed mode, c b 400 pf 20 160 t fcl scl fall time standard mode 20+0.1c b 300 ns fast mode 20+0.1c b 300 fast mode plus 20+0.1c b 120 high ? speed mode, c b 100 pf 10 40 high ? speed mode, c b 400 pf 20 80 t rcl1 rise time of scl after a re- peated start condition and af- ter ack bit high ? speed mode, c b 100 pf 10 80 ns high ? speed mode, c b 400 pf 20 160 t rda sda rise time standard mode 20+0.1c b 1000 ns fast mode 20+0.1c b 300 fast mode plus 20+0.1c b 120 high ? speed mode, c b 100 pf 10 80 high ? speed mode, c b 400 pf 20 160 t fda sda fall time standard mode 20+0.1c b 300 ns fast mode 20+0.1c b 300 fast mode plus 20+0.1c b 120 high ? speed mode, c b 100 pf 10 80 high ? speed mode, c b 400 pf 20 160 t su;sto stop condition setup time standard mode 4 s fast mode 600 ns fast mode plus 120 high ? speed mode 160 c b capacitive load for sda and scl 400 pf
fan53526 www. onsemi.com 8 timing diagrams ?? ?? ?? ?? ?? ?? ?? ?? start ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? figure 3. i 2 c interface timing for fast plus, fast, and slow modes ?? ?? ?? ?? ?? ???? ???? repeated start ??? ??? ? up = r p resistor pull ? up note a note a: first rising edge of sclh after repeated start and after each ack bit. t hd;sta t su;sta figure 4. i 2 c interface timing for high ? speed mode
fan53526 www. onsemi.com 9 typical characteristics (unless otherwise specified, auto pfm/pwm mode, v in = 3.6 v, v out = 1.15625v, vsel = en = v in , t a = 25 c; circuit and components according to figure 1 and table 2. efficiency test conditions; i load : 1 ma to 3 a, l = 330 nh, dfe201612e ? r33n (toko). c in = 4.7 f, 0603, c1608x5r1a475k (tdk), c out x 2 = 2x47 f, 0603, grm188r60j476me (murata).) figure 5. efficiency vs. load current and input voltage, v out =1.15625v figure 6. efficiency vs. load current and temperature, v in =3.6v, v out =1.15625v figure 7. output regulation vs. load current and input voltage, v out =1.15625v figure 8. pwm entry / exit level vs. input voltage, v out =1.15625v figure 9. output ripple vs. load current, v in =4.2v and 3.6v, v out =1.15625v, auto and forced pwm figure 10. frequency vs. load current, v in =4.2v and 3.6v, v out =1.15625v, auto pwm
fan53526 www. onsemi.com 10 typical characteristics (continued) (unless otherwise specified, auto pfm/pwm mode, v in = 3.6 v, v out = 1.15625v, vsel = en = v in , t a = 25 c; circuit and components according to figure 1 and table 2. efficiency test conditions; i load : 1 ma to 3 a, l = 330 nh, dfe201612e ? r33n (toko). c in = 4.7 f, 0603, c1608x5r1a475k (tdk), c out x 2 = 2x47 f, 0603, grm188r60j476me (murata).) figure 11. quiescent current vs. input voltage and temperature, auto mode, v out =1.15625v figure 12. efficiency vs. load current and temperature, v in =3.6v, v out =1.15625v vin vout figure 13. line transient, 3.6 ? 4.2 v in , 1.15625 v out , 10 s edge at 1 a load iout vout figure 14. load transient, 3.6 v in , 1.15625 v out , 0.01 ? 1.5 a, 120 ns edge en vout figure 15. startup, 5 load, v out = 1.15625 v, v in = 3.6 v iout vout figure 16. load transient, 3.6 v in , 1.15625 v out , 1.5 ? 3 a, 120 ns edge
fan53526 www. onsemi.com 11 typical characteristics (continued) (unless otherwise specified, auto pfm/pwm mode, v in = 3.6 v, v out = 1.15625v, vsel = en = v in , t a = 25 c; circuit and components according to figure 1 and table 2. efficiency test conditions; i load : 1 ma to 3 a, l = 330 nh, dfe201612e ? r33n (toko). c in = 4.7 f, 0603, c1608x5r1a475k (tdk), c out x 2 = 2x47 f, 0603, grm188r60j476me (murata).) iout (9500ma/div) 0ma 500ma vout (10mv/div) 0.6v offset 618mv + 16mv ? 16mv 582mv figure 17. load transient, 3.8 v in , 0.6 v out , 0 ? 500 ma, 100 ns edge, 47 f c out operating description the fan53526 is a step ? down switching voltage regulator that delivers a programmable output voltage from an input voltage supply of 2.5 v to 5.5 v. using a proprietary architecture with synchronous rectification, the fan53526 is capable of delivering 3.0 a at over 80% efficiency. the regulator operates at a nominal frequency of 2.4 mhz at full load, which reduces the value of the external components to 330 nh or 470 nh for the output inductor and 44 f for the output capacitor . high efficiency is maintained at light load with single ? pulse pfm. an i 2 c ? compatible interface allows transfers up to 3.4 mbps. this communication interface can be used to: ? dynamically re ? program the output voltage in 6.25 mv increments; ? reprogram the mode to enable or disable pfm; ? control voltage transition slew rate; or ? enable / disable the regulator. control scheme the fan53526 uses a proprietary non ? linear, fixed ? frequency pwm modulator to deliver a fast load transient response, while maintaining a constant switching frequency over a wide range of operating conditions. the regulator performance is independent of the output capacitor esr, allowing for the use of ceramic output capacitors. although this type of operation normally results in a switching frequency that varies with input voltage and load current, an internal frequency loop holds the switching frequency constant over a large range of input voltages and load currents. for very light loads, the fan53526 operates in discontinuous current mode (dcm) single ? pulse pfm, which produces low output ripple compared with other pfm architectures. transition between pwm and pfm is relatively seamless, providing a smooth transition between dcm and ccm modes. pfm can be disabled by programming the mode bits in the control register in combination with the state of the vsel pin . see table in the control register, 02h. enable and soft ? start when the en pin is low; the ic is shut down, all internal circuits are off, and the part draws very little current. in this state, i 2 c can be written to or read from as long as input voltage is above the uvlo. the registers keep the content when the en pin is low. the registers are reset to default values during a power on reset (por). when the output_discharge bit in the control register is enabled (logic high) and the en pin is low or the buck_enx bit is low, an 11 w load is connected from vout to gnd to discharge the output capacitors. raising en while the buck_enx bit is high activates the part and begins the soft ? start cycle. during soft ? start, the modulator?s internal reference is ramped slowly to minimize surge currents on the input and prevent overshoot of the output voltage. synchronous rectification is inhibited, allowing the ic to start into a pre ? charged capacitive load. if large values of output capacitance are used, the regulator may fail to start. the maximum c out capacitance for starting with a heavy constant ? current load is approximately:
fan53526 www. onsemi.com 12 c outmax (i lmpk i load ) 320 v out (eq. 1) where c outmax is expressed in f and i load is the load current during soft ? start, expressed in a. if the regulator is at its current limit for 16 consecutive current limit cycles, the regulator shuts down and enters tri ? state before reattempting soft ? start 1700 s later. this limits the duty cycle of full output current during soft ? start to prevent excessive heating. the ic allows for software enable of the regulator, when en is high, through the buck_en bits. buck_en0 and buck_en1 are both initialized high. these options start after a por , regardless of the state of the vsel pin. table 10. hardware and software enable pins bits en vsel buck_en0 buck_en1 output mode 0 x x x off shutdown 1 0 0 x off shutdown 1 0 1 x on auto 1 1 x 0 off shutdown 1 1 x 1 on fpwm vsel pin and i 2 c programming output voltage the output voltage is set by the nselx control bits in vsel0 and vsel1 registers. the output is given as: v out 0.600v nselx 6.25mv (eq. 2) for example, if nsel =1010000 (80 decimal), then v out = 0.600 + 0.5 = 1.100 v. output voltage can also be controlled by toggling the vsel pin low or high. vsel low corresponds to vsel0 and vsel high corresponds to vsel1. upon por, vsel0 and vsel1 are reset to their default voltages , as shown in table 8. transition slew rate limiting when transitioning from a low to high voltage, the ic can be programmed for one of eight possible slew rates using the slew bits in the control register, as shown in table 5 . table 11. transition slew rate decimal bin slew rate 0 000 64.00 mv/ s 1 001 32.00 mv/ s 2 0 1 0 16.00 mv/ s 3 011 8.00 mv/ s 4 100 4.00 mv/ s 5 101 2.00 mv/ s 6 110 1.00 mv/ s 7 111 0.50 mv/ s transitions from high to low voltage rely on the output load to discharge v out to the new set point. once the high ? to ? low transition begins, the ic stops switching until v out has reached the new set point. under ? voltage lockout (uvlo) when en is high, the under ? voltage lockout keeps the part from operating until the input supply voltage rises high enough to properly operate. this ensures proper operation of the regulator during startup or shutdown. input over ? voltage protection (ovp) when v in exceeds v sdwn (~ 6.2 v) , the ic stops switching to protect the circuitry from internal spikes above 6.5 v. an internal filter prevents the circuit from shutting down due to noise spikes. current limiting a heavy load or short circuit on the output causes the current in the inductor to increase until a maximum current threshold is reached in the high ? side switch. upon reaching
fan53526 www. onsemi.com 13 this point, the high ? side switch turns off, preventing high currents from causing damage. 16 consecutive current limit cycles in current limit , cause the regulator to shut down and stay off for about 1700 s before attempting a restart. thermal shutdown when the die temperature increases, due to a high load condition and/or high ambient temperature, the output switching is disabled until the die temperature falls sufficiently. the junction temperature at which the thermal shutdown activates is nominally 150 c with a 17 c hysteresis. monitor register (reg05) the monitor register indicates of the regulation state of the ic. if the ic is enabled and is regulating, its value is (1000 0001). i 2 c interface the serial interface is compatible with standard, fast, fast plus, and hs mode i 2 c bus specifications. the scl line is an input and its sda line is a bi ? directional open ? drain output; it can only pull down the bus when active. the sda line only pulls low during data reads and when signaling ack. all data is shifted in msb (bit 7) first. i 2 c slave address in hex notation, the slave address assumes a 0 ls bit. the hex slave address is c0 for all options except fan53526uc168x, which has a hex slave address of c2. table 12. i 2 c slave address hex bits 7 6 5 4 3 2 1 0 c0 1 1 0 0 0 0 0 c2 1 1 0 0 0 0 1 other slave addresses can be assigned. contact an on semiconductor representative. bus timing as shown in figure 18 data is normally transferred when scl is low. data is clocked in on the rising edge of scl. typically, data transitions shortly at or after the falling edge of scl to allow sufficient time for the data to set up before the next scl rising edge. scl t su t h sda data change allowed figure 18. data transfer timing each bus transaction begins and ends with sda and scl high. a transaction begins with a st art condition, which is defined as sda transitioning from 1 to 0 with scl high, as shown in figure 19. scl t hd;sta sda slave address ms bit figure 19. start bit a transaction ends with a stop condition, defined as sda transitioning from 0 to 1 with scl high, as shown in figure 20. scl sda slave releases master drives ack(0) or nack(1) t hd;sto figure 20. stop bit during a read from the fan53526, the master issues a repeated start after sending the register address and before resending the slave address. the repeated start is a 1 to 0 transition on sda while scl is high, as shown in figure 21 .
fan53526 www. onsemi.com 14 scl sda ack(0) or nack(1) slave releases sladdr ms bit t hd;sta t su;sta figure 21. repeated start timing high ? speed (hs) mode the protocols for high ? speed (hs), low ? speed (ls), and fast ? speed (fs) modes are identical; except the bus speed for hs mode is 3.4 mhz. hs mode is entered when the bus master sends the hs master code 00001xxx after a start condition (figure 19). the master code is sent in fast or fast ? plus mode (less than 1 mhz clock); slaves do not ack this transmission. the master generates a repeated start condition (figure 21) that causes all slaves on the bus to switch to hs mode. the master then sends i 2 c packets, as described above, using the hs mode clock rate and timing. the bus remains in hs mode until a st op bit (figure 20) is sent by the master. while in hs mode, packets are separated by repeated start conditions (figure 21). read and write transactions the following figures outline the sequences for data read and write. bus control is signified by the shading of the packet, defined as: ? master drives bus and ? slave drives bus all addresses and data are msb first. table 13. i 2 c bit definitions for figure 22 and figure 23 symbol definition s start, see figure 19 p stop, see figure 20 r repeated start, see figure 21 a ack. the slave drives sda to 0 acknowledge the preceding packet. a nack. the slave sends a 1 to nack the preceding packet. s slave address a reg addr a a p 0 7 bits 8 bits 8 bits data 000 figure 22. write transaction s slave address a reg addr a 0 7 bits 8 bits r slave address 7 bits 1 a data a 8 bits 00 01 p figure 23. write transaction followed by a read transaction
fan53526 www. onsemi.com 15 register description table 14. register map hex address name function binary hex 00 vsel0 controls v out settings when vsel pin = low 1xxxxxxx xx 01 vsel1 controls v out settings when vsel pin = high 1xxxxxxx xx 02 control determines whether v out output discharge is enabled and also the slew rate of positive transitions 10000010 82 03 id1 read ? only register identifies vendor and chip type 1000 000 1 81 04 id2 read ? only register identifies die revision 00001000 08 05 monitor indicates device status 00000000 00 table 15. bit definitions bit name type value description vsel0 register address: 00 7 buck_en0 r/w 1 software buck enable. when en pin is low, the regulator is off. when en pin is high, buck_en bit takes precedent. 6:0 nsel0 r/w xxx xxxx sets v out value from 0.600 to 1.39375 v (see eq.2). vsel1 register address: 01 7 buck_en1 r/w 1 software buck enable. when en pin is low, the regulator is off. when en pin is high, buck_en bit takes precedent. 6:0 nsel1 r/w xxx xxxx sets v out value from 0.600 to 1.39375 v (see eq.). control register address: 02 7 output_ discharge r/w 0 when the regulator is disabled, v out is not discharged. 1 when the regulator is disabled, v out discharges through an internal pull ? down. 6:4 slew r/w 000 ?111 sets the slew rate for positive voltage transitions (see table 4) 3 reserved 0 always reads back 0. 2 reset r/w 0 setting to 1 resets all registers to default values. always reads back 0. 1:0 mode r/w 10 in combination with the vsel pin, these two bits set the opera- tion of the buck to be either in auto ? pfm/pwm mode during light load or forced pwm mode. see table below. mode of operation vsel pin binary operation low x0 auto pfm/pwm low x1 forced pwm high 0x auto pfm/pwm high 1x forced pwm id1 register address: 03 7:5 vendor r 100 signifies on semiconductor as the ic vendor. 4 reserved r 0 always reads back 0. 3:0 die_id r 000 1 die id ? fan53525/6. id2 register address: 04 7:4 reserved r 0000 always reads back 0000. 3:0 die_rev r 1 000 fan53526 die revision monitor register address: 05 7 pgood r 0 1: buck is enabled and soft ? start is completed.
fan53526 www. onsemi.com 16 table 15. bit definitions bit description value type name 6 uvlo r 0 1: signifies the vin is less than the uvlo threshold. 5 ovp r 0 1: signifies the vin is greater than the ovp threshold. 4 pos r 0 1: signifies a positive voltage transition is in progress and the output voltage has not yet reached its new setpoint. 3 neg r 0 1: signifies a negative voltage transition is in progress and the output voltage has not yet reached its new setpoint. 2 reset ? stat r 0 1: indicates that a register reset was performed. this bit is cleared after register 5 is read. 1 ot r 0 1: signifies the vin is less than the uvlo threshold. 0 buck_status r 0 1: signifies the vin is greater than the ovp threshold. application information selecting the inductor the output inductor must meet both the required inductance and the energy ? handling capability of the application. the inductor value affects the average current limit, the output voltage ripple, and the efficiency. the ripple current ( i) of the regulator is: i v out v in v in v out l f sw (eq. 3) the maximum average load current, i max(load), is related to the peak current limit, i lim(pk) , by the ripple current such that: i max(load) i lim(pk) i 2 (eq. 4) the fan53526 is optimized for operation with l=330 nh, but is stable with inductances up to 1.0 h (nominal). the inductor should be rated to maintain at least 80% of its value at i lim(pk) . failure to do so decreases the amount of dc current the ic can deliver. efficiency is af fected by the inductor dcr and inductance value. decreasing the inductor value for a given physical size typically decreases the dcr; but since i increases, the rms current increases, as do core and skin ? effect losses: i rms i out(dc) 2 i 2 12 (eq. 5) the increased rms current produces higher losses through the r ds(on) of the ic mosfets and the inductor esr. increasing the inductor value produces lower rms currents, but degrades transient response. for a given physical inductor size, increased inductance usually results in an inductor with lower saturation current. the increased rms current produces higher losses through the r ds(on) of the ic mosfets and the inductor esr. increasing the inductor value produces lower rms currents, but degrades transient response. for a given physical inductor size, increased inductance usually results in an inductor with lower saturation current. table 16. effects of inductor value (from 330nh recommended) on regulator performance i max(load) v out (eq.(7)) transient response increase decrease degraded inductor current rating the current - limit circuit can allow substantial peak currents to flow through l1 under worst ? case conditions. if it is possible for the load to draw such currents, the inductor should be capable of sustaining the current or failing in a safe manner. for space ? constrained applications, a lower current rating for l1 can be used. the fan53526 may still protect these inductors in the event of a short circuit, but may not be able to protect the inductor from failure if the load is able to draw higher currents than the dc rating of the inductor. refer to table 2 for the recommended inductors. output capacitor and v out ripple if space is at a premium , 0603 capacitors may be used. increasing c out has negligible effect on loop stability and can be increased to reduce output voltage ripple or to improve transient response. output voltage ripple, v out , is calculated by: v out i l
f sw c out esr 2 2 d (1 d) 1 8 f sw c out (eq. 6) where c out is the effective output capacitance.
fan53526 www. onsemi.com 17 the capacitance of c out decreases at higher output voltages, which results in higher v out . equation 6 is only valid for ccm operation, which occurs in pwm mode. the fan53526 can be used with either 2 x 22 f (0603) or 2 x 47 f (0603) output capacitor configuration. if a tighter ripple and transient specification is need from the fan53526, then the 2 x 47 f is recommended. the lo west v out is obtained when the ic is in pwm mode and, therefore, operating at 2.4 mhz. in pfm mode, f sw is reduced, causing v out to increase. esl effects the equivalent series inductance (esl) of the output capacitor network should be kept low to minimize the square ? wave component of output ripple that results from the division ratio c out esl and the output inductor (l out ). the square ? wave component due to the esl can be estimated as: v out(sq) v in esl cout l1 (eq. 7) a good practice to minimize this ripple is to use multiple output capacitors to achieve the desired c out value. for example, to obtain c out =20 f, a single 22 f 0805 would produce twice the square wave ripple as two x 10 f 0805. to minimize esl, try to use capacitors with the lowest ratio of length to width. 0805 s have lower esl than 1206 s. if low output ripple is a chief concern, some vendors produce 0508 capacitors with ultra ? low esl. placing additional small ? value capacitors near the load also reduces the high ? frequency ripple components. input capacitor the ceramic input capacitors should be placed as close as possible between the vin and pgnd pins to minimize the parasitic inductance. if a long wire is used to bring power to the ic, additional ?bulk? capacitance (electrolytic or tantalum) should be placed between cin and the power source lead to reduce under ? damped ringing that can occur between the inductance of the power source leads and c in . thermal considerations heat is removed from the ic through the solder bumps to the pcb copper. the junction ? to ? ambient thermal resistance ( ja ) is largely a function of the pcb layout (size, copper weight, and trace width) and the temperature rise from junction to ambient ( t). for the fan53526, ja is 42 c/w when mounted on its four ? layer with vias evaluation board in still air with 2 oz. outer layer copper weight and 1 oz. inner layer. for long ? term reliable operation, the junction temperature (t j ) should be maintained below 125 c. to calculate maximum operating temperature (<125 c) for a specific application: 1. use efficiency graphs to determine efficiency for the desired v in , v out , and load conditions. 2. calculate total power dissipation using: p t v out i load 1 1 (eq. 8) 3. estimate inductor copper losses using: p l i load 2 dcr l (eq. 9) 4. determine ic losses by removing inductor losses (step 3) from total dissipation: p ic p t p l (eq. 10) 5. determine device operating temperature: t p ic ja t ic t a t (eq. 11) and note that the r ds(on) of the power mosfets increases linearly with temperature at about 1.4%/ c. this causes the efficiency ( ) to degrade with increasing die temperature. layout recommendations 1. the input capacitor (c in ) should be connected as close as possible to the vin and gnd pins. connect to vin and gnd using only top metal. do not route through via (see figure 24). 2. place the inductor (l) as close as possible to the ic. use short wide traces for the main current paths. 3. the output capacitor (c out ) should be as close as possible to the ic. connection to gnd should only be on top metal. feedback signal connection to vout should be routed away from noisy components and traces (e.g. sw line) (see figure 26).
fan53526 www. onsemi.com 18 figure 24. guidance for layer 1 figure 25. layer 2
fan53526 www. onsemi.com 19 figure 26. layer 3 figure 27. layer 4 table 17. product ? specific dimensions d e x y 2.015 0 03 mm 1.310 0.03 mm 0.255 mm 0.2075 mm
fan53526 www. onsemi.com 20 c fan5352 6 en sda scl vsel fan53526 pvin vout sw pgnd agnd c in1 c in gnd v do core processor (system load) c out 1. fb trace connects to ?+? side of cout cap. 2. do not place cout near fan53526, place cout near load. 3. maximum trace resistance between the inductor and the load should not exceed 30m . for a 20 mils wide pcb trace with 0.5mils thickness using 2oz. copper, a length of 0.5 inches gives a resistance of 24.3m . l1 figure 28. remote sensing schematic
fan53526 www. onsemi.com 21 wlcsp15 2.015x1.31x0.586 case 567qs issue o
fan53526 www. onsemi.com 22 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 fan53526/d tinybuck is registered trademark of semiconductor components industries, llc (scillc) or its subsidiaries in the united states and/or other countries. arm is a registered trademark of arm limited (or its subsidiaries) in the eu and/or elsewhere. tegra is a trademark of nvidia corporation. omap is a trademark and brand of texas instruments incorporated. novathor is a trademark of st ? ericsson. armada is a trademark of emergency technology, inc. krait is a trademark of qualcomm incorporated. literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ?

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